Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

被引：11
|
作者：
Hariyama, M [1 ]
Sasaki, H [1 ]
Kameyama, M [1 ]
机构：
[1] Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808579, Japan
来源：
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 2005年 / E88D卷 / 07期
关键词：
stereo vision; SAD (sum of absolute differences); memory allocation; logic-in-memory architecture;
D O I：
10.1093/ietisy/e88-d.7.1486
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.
引用
收藏
页码：1486 / 1491
页数：6
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