VLSI architecture for MRF based stereo matching

被引：0

作者：

Park, Sungchan ^{[1
]}

Chen, Chao ^{[1
]}

Jeong, Hong ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol, Pohang 790784, Kyungbuk, South Korea

来源：

EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION - PROCEEDINGS | 2007年 / 4599卷

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

As a step towards real-time stereo on 2D markov random field (MRF), we will present fast belief propagation (FBP) VLSI architecture for stereo matching, which has a parallel, distributed and memory-efficient structure and lowest error rates among the real-time systems. FBP can reduce memory complexities by 17 times smaller than belief propagation (BP) and output 320x240 disparity image of 32 levels with 320 parallel processors on 2 Xilinx FPGAs at 30 frames/s. Multiple chips can be cascaded to increase computation speed due to its linear array architecture. Our structure is more adequate for high resolution and real-time applications like 3D video conference, multi-view coding and 3D modelling.

引用

页码：55 / +

页数：2

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