VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture

被引：10

作者：

Hariyama, M ^{[1
]}

Kameyama, M ^{[1
]}

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Aoba Ku, Sendai, Miyagi 9808579, Japan

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346545

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a VLSI processor for reliable stereo matching to establish correspondence between images by selecting a desirable window size for sum of absolute differences(SAD) computation. In SAD computation, a degree of parallelism between pixels in a window changes depending on its window size, while a degree of parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is also proposed to achieve 100% utilization of processing elements. Not only 100% utilization but also a simple interconnection network between memory modules and processing elements makes the VLSI processor much superior to the pixel-parallel-architecture-based VLSI processors.

引用

页码：166 / 169

页数：4

共 45 条

[1] Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access
Hariyama, M
Sasaki, H
Kameyama, M
[J]. 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2004, : 245 - 247
[2] Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access
Hariyama, M
Sasaki, H
Kameyama, M
[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2005, E88D (07): : 1486 - 1491
[3] VLSI processor for reliable stereo matching based on adaptive window-size selection
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[4] FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture
Hariyama, M
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[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (12) : 3516 - 3522
[5] Challenge of MTJ/MOS-Hybrid Logic-in-Memory Architecture for Nonvolatile VLSI Processor
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[J]. 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 117 - 120
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[J]. JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2005, 11 (5-6) : 619 - 632
[7] VLSI architecture for MRF based stereo matching
Park, Sungchan
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[J]. EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION - PROCEEDINGS, 2007, 4599 : 55 - +
[8] Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm
Hanyu, Takahiro
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Onizawa, Naoya
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[J]. 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 1006 - +
[9] Highly-parallel stereo vision VLSI processor based on arm optimal parallel memory access scheme
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[J]. IEICE TRANSACTIONS ON ELECTRONICS, 2001, E84C (03): : 382 - 389
[10] Crossbar-Based Memristive Logic-in-Memory Architecture
Papandroulidakis, Georgios
Vourkas, Ioannis
Abusleme, Angel
Sirakoulis, Georgios Ch.
Rubio, Antonio
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (03) : 491 - 501

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