VLSI architecture of a high performance parallel FFT processor

被引：0

作者：

Wan, HX ^{[1
]}

Gao, ZB ^{[1
]}

Chen, H ^{[1
]}

机构：

[1] Sch Informat Sci & Technol, Dept Elect Engn, Beijing 100081, Peoples R China

来源：

ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 8 | 2005年

关键词：

FFT; butterfly-unit; block-floating-point; pipelined;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Through the study of the character of radix-2 and radix-4 Decimation-in-time FFT algorithm, a kind of high performance FFT/IFFT processor is proposed. With modified radix-4 butterfly unit it can process a length - N computation where N is power of 2, which can remarkably reduce needed resource. The processor allows conflict-free access of the 4 operands distributed over parallel memory modules, which can obviously increase process speed The structure of the controlling unit is easily to be designed in module. In this paper detail description of algorithm and frame chart are also introduced.

引用

页码：472 / 478

页数：7

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