A Low-Power Area-Efficient Design and Comparative Analysis for High-Resolution Neural Data Compression

被引:0
|
作者
Ashraf, Mohammed [1 ]
Mostafa, Hassan [1 ,2 ]
El-Adawy, Ahmed A. [1 ]
机构
[1] Cairo Univ, Elect & Commun Engn Dept, Giza 12613, Egypt
[2] AUC & Zewail City Sci & Technol, Ctr Nanoelect & Devices, New Cairo 11835, Egypt
基金
加拿大自然科学与工程研究理事会;
关键词
Neural Signals; Multichannel Neural Recording; Data Compression; Image processing; Low-power Design; HW Implementation;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Nowadays, brain scientific research progress depends on signal compression at high spatial resolutions, for efficient storage and low-rate transmission through wireless connection to outside world. So that neural data compression at the implant site is necessary in order to conform with the wireless rates restrictions. In this paper, the high spatial correlation is utilized to increase the data compression ratio. Then we investigate and compare three different proposed low-power image compression algorithms based on discrete cosine transform (DCT) and discrete wavelet transform (DWT) to provide the best trade-off between hardware complexity and compression performance. Hence, we conclude that Adaptive 2D-DWT algorithm is a promising solution for low-power implantable devices.
引用
收藏
页码:217 / 220
页数:4
相关论文
共 50 条
  • [41] Low-power and area-efficient FIR filter implementation suitable for multiple taps
    Kim, KS
    Lee, K
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (01) : 150 - 153
  • [42] A low-power and area-efficient quaternary adder based on CNTFET switching logic
    Shirin Fakhari
    Narges Hajizadeh Bastani
    Mohammad Hossein Moaiyeri
    Analog Integrated Circuits and Signal Processing, 2019, 98 : 221 - 232
  • [43] Low-power area-efficient decimation filters in sigma-delta ADCs
    Yi, Feng
    Wu, Xiaobo
    Xu, Jian
    EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 833 - 836
  • [44] A Low-Power Area-Efficient 8 bit SAR ADC Using Dual Capacitor Arrays for Neural Microsystems
    Chang, Sun-Il
    Yoon, Euisik
    2009 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-20, 2009, : 1647 - 1650
  • [45] A design method and developments of a low-power and high-resolution multiphase generation system
    Matsumoto, Akinori
    Sakiyama, Shiro
    Tokunaga, Yusuke
    Morie, Takashi
    Dosho, Shiro
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) : 831 - 843
  • [46] Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis
    S., Haroon Rasheed
    Nelapati, Rajeev Pankaj
    PLOS ONE, 2024, 19 (03):
  • [47] A low-power CAM design for LZ data compression
    Lin, KJ
    Wu, CW
    IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (10) : 1139 - 1145
  • [48] A low-power technique for high-resolution dynamic comparators
    Khorami, Ata
    Sharifkhani, Mohammad
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2018, 46 (10) : 1777 - 1795
  • [49] HIGH-RESOLUTION LOW-POWER CMOS D/A CONVERTER
    YANG, JW
    MARTIN, KW
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) : 1458 - 1461
  • [50] An area-efficient low-power SCM topology for high performance network-on Chip (NoC) architecture using an optimized routing design
    Poovendran, R.
    Sumathi, S.
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2019, 31 (14):