A Low-Power Area-Efficient Design and Comparative Analysis for High-Resolution Neural Data Compression

被引：0
|
作者：
Ashraf, Mohammed [1 ]
Mostafa, Hassan [1 ,2 ]
El-Adawy, Ahmed A. [1 ]
机构：
[1] Cairo Univ, Elect & Commun Engn Dept, Giza 12613, Egypt
[2] AUC & Zewail City Sci & Technol, Ctr Nanoelect & Devices, New Cairo 11835, Egypt
来源：
2016 28TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (ICM 2016) | 2016年
基金：
加拿大自然科学与工程研究理事会;
关键词：
Neural Signals; Multichannel Neural Recording; Data Compression; Image processing; Low-power Design; HW Implementation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Nowadays, brain scientific research progress depends on signal compression at high spatial resolutions, for efficient storage and low-rate transmission through wireless connection to outside world. So that neural data compression at the implant site is necessary in order to conform with the wireless rates restrictions. In this paper, the high spatial correlation is utilized to increase the data compression ratio. Then we investigate and compare three different proposed low-power image compression algorithms based on discrete cosine transform (DCT) and discrete wavelet transform (DWT) to provide the best trade-off between hardware complexity and compression performance. Hence, we conclude that Adaptive 2D-DWT algorithm is a promising solution for low-power implantable devices.
引用
收藏
页码：217 / 220
页数：4
相关论文
共 50 条
  • [31] Low-power High-resolution Telemetry System
    Mikhaylyuk, Alexey
    Silantev, Alexander
    Zosimov, Vladislav
    Savchenko, Yurij
    PROCEEDINGS OF THE 2018 IEEE CONFERENCE OF RUSSIAN YOUNG RESEARCHERS IN ELECTRICAL AND ELECTRONIC ENGINEERING (EICONRUS), 2018, : 1397 - 1400
  • [32] Low-Power High-Resolution 32-channel Neural Recording System
    Yun, Xiao
    Kim, Donghwi
    Stanacevic, Milutin
    Mainen, Zachary
    2007 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-16, 2007, : 2373 - +
  • [33] Low-power area-efficient pipelined A/D converter design using a single-ended amplifier
    Miyazaki, D
    Kawahito, S
    Tadokoro, Y
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (02) : 293 - 300
  • [34] A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation
    Zhong, Xiaopeng
    Bermak, Amine
    Tsui, Chi-Ying
    2017 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2017, : 148 - 153
  • [35] Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier
    Daisuke Miyazaki
    Shoji Kawahito
    Analog Integrated Circuits and Signal Processing, 2000, 25 : 235 - 244
  • [36] Low-power area-efficient pipelined A/D converter design using a single-ended amplifier
    Miyazaki, D
    Kawahito, S
    Tadokoro, Y
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2000, 25 (03) : 235 - 244
  • [37] Design of a Low-Power and Area-Efficient LDO Regulator Using a Negative-R-Assisted Technique
    Kim, Jung Sik
    Javed, Khurram
    Roh, Jeongjin
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (10) : 3892 - 3896
  • [38] Fast Fourier transform processor based on low-power and area-efficient algorithm
    Oh, JY
    Lim, MS
    PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 198 - 201
  • [39] A low-power and area-efficient quaternary adder based on CNTFET switching logic
    Fakhari, Shirin
    Bastani, Narges Hajizadeh
    Moaiyeri, Mohammad Hossein
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 98 (01) : 221 - 232
  • [40] Pre-charge solution for low-power, area-efficient SAR ADC
    Sarafi, Sahar
    Bin Aain, Abu Khari
    Bargoshadi, Javad Abbaszadeh
    Chegini, Amin
    IEICE ELECTRONICS EXPRESS, 2015, 12 (20):
12345