Layout geometry impact on nLDMOS devices for high-voltage ESD protection

被引：1

作者：

Yan, Yongming ^{[1
]}

Wang, Yang ^{[2
]}

Zeng, Yun ^{[1
]}

Jin, Xiangliang ^{[2
]}

机构：

[1] Hunan Univ, Sch Phys & Elect, Changsha 410082, Hunan, Peoples R China

[2] Xiangtan Univ, Sch Phys & Optoelect, Xiangtan 411105, Hunan, Peoples R China

来源：

ELECTRONICS LETTERS | 2015年 / 51卷 / 23期

基金：

中国国家自然科学基金;

关键词：

D O I：

10.1049/el.2015.2156

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

N-channel, lateral, double-diffused MOS (NLDMOS) devices with finger-type, square-type, and octagon-type layout styles are investigated and fabricated in a 0.5-mu m 18 V CMOS-DMOS (CDMOS) process. The square-type nLDMOS achieves the highest ESD failure current of 4.7 A and is also the device occupying the smallest chip area among the three layout styles. In view of the area efficiency, the square-type structure provides more than 30 and 25% higher current handling capability per area than the traditional finger-type and octagonal-type structures, respectively. Because of its better area efficiency, the square-type structure is a promising layout for nLDMOS in highvoltage ESD protection applications.

引用

页码：1902 / 1903

页数：2

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