Quadruple voltage mixed quenching and active resetting circuit in 150 nm CMOS for an external SPAD

被引：0
|
作者：
Dervic, Alija [1 ]
Goll, Bernhard [1 ]
Zimmermann, Horst [1 ]
机构：
[1] Vienna Univ Technol, Inst Electrodynam Mircowave & Circuit Engn, Vienna, Austria
来源：
2020 23RD INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2020) | 2020年
关键词：
mixed quenching circuit; active resetting circuit; SPAD; photon counting; CMOS; dead-time controllability;
D O I：
10.1109/ddecs50862.2020.9095565
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An integrated quadruple voltage mixed quenching, and active resetting circuit (Q(2)RC) in a 150 nm CMOS process is presented in this paper. The Q(2)RC features an excess-bias voltage of 7.2 V, which is four times the 1.8 V supply voltage. The dead time can be adjusted from 7 ns to 29 ns, which corresponds to the count rate range from 34 Mcps to 142 Mcps. Post-layout simulation results for an external SPAD with an equivalent parasitic capacitance of 4 pF are reported. The achieved quenching time of the Q(2)RC is 1.75 ns, which results in 4.05 GV/s quenching slew rate, while the delay time is 1.1 ns, and the resetting time is 2.55 ns.
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页数：5
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