Quadruple voltage mixed quenching and active resetting circuit in 150 nm CMOS for an external SPAD

An integrated quadruple voltage mixed quenching, and active resetting circuit (Q(2)RC) in a 150 nm CMOS process is presented in this paper. The Q(2)RC features an excess-bias voltage of 7.2 V, which is four times the 1.8 V supply voltage. The dead time can be adjusted from 7 ns to 29 ns, which corresponds to the count rate range from 34 Mcps to 142 Mcps. Post-layout simulation results for an external SPAD with an equivalent parasitic capacitance of 4 pF are reported. The achieved quenching time of the Q(2)RC is 1.75 ns, which results in 4.05 GV/s quenching slew rate, while the delay time is 1.1 ns, and the resetting time is 2.55 ns.