Reliability of ultra thin gate oxide CMOS devices: Design perspective

被引：0
|
作者：
Parthasarathy, C. R. [1 ,3 ]
Denais, M. [1 ]
Huard, V. [2 ]
Ribes, G. [1 ]
Vincent, E. [1 ]
Bravaix, A. [3 ]
机构：
[1] STMicroelect, 850,Rue Jean Monet, F-38926 Crolles, France
[2] Philips Semicond, F-38926 Crolles, France
[3] UMR CNRS 6137, Maison Technol, L2MP ISEN, F-83000 Toulon, France
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective-in terms of characterization, mechanisms and circuit analysis-introducing assessment of multiple degradation modes on same device.
引用
收藏
页码：122 / +
页数：3
相关论文
共 50 条
  • [1] Hot-carrier reliability of ultra-thin gate oxide CMOS
    Momose, HS
    Nakamura, S
    Ohguro, T
    Yoshitomi, T
    Morifuji, E
    Morimoto, T
    Katsumata, Y
    Iwai, H
    SOLID-STATE ELECTRONICS, 2000, 44 (11) : 2035 - 2044
  • [2] Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits
    Stathis, JH
    39TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 2001, 2001, : 132 - 149
  • [3] Investigation on Thin Gate Oxide Behavior for CMOS Devices
    Liu, Mingyuan
    He, Yonggen
    Hung, Albert
    Liu, Yunzhen
    Liu, Bingwu
    Zhou, Dibao
    Zheng, Kai
    Liu, Jinghua
    Ju, Jianhua
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1154 - 1157
  • [4] Ultra-thin gate oxide reliability projections
    Weir, BE
    Alam, MA
    Silverman, PJ
    Baumann, F
    Monroe, D
    Bude, JD
    Timp, GL
    Hamad, A
    Ma, Y
    Brown, MM
    Hwang, D
    Sorsch, TW
    Ghetti, A
    Wilk, GD
    SOLID-STATE ELECTRONICS, 2002, 46 (03) : 321 - 328
  • [5] Reliability and integration of ultra-thin gate dielectrics for advanced CMOS
    Buchanan, DA
    Lo, SH
    MICROELECTRONIC ENGINEERING, 1997, 36 (1-4) : 13 - 20
  • [6] Influence of carbon contamination on ultra thin gate oxide reliability
    Iwamoto, T
    Miyake, T
    Ohmi, T
    MICROELECTRONIC DEVICE AND MULTILEVEL INTERCONNECTION TECHNOLOGY II, 1996, 2875 : 207 - 215
  • [7] Ultra-thin gate oxide technology for high performance CMOS
    Momose, HS
    Nakamura, S
    Katsumata, Y
    Iwai, H
    ULSI SCIENCE AND TECHNOLOGY / 1997: PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM ON ULTRALARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY, 1997, 1997 (03): : 235 - 246
  • [8] Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide
    Lin, CH
    Kuo, JB
    Su, KW
    Liu, S
    ELECTRONICS LETTERS, 2006, 42 (03) : 182 - 184
  • [9] An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices
    Chen, SJ
    Lin, TC
    Lo, DK
    Yang, JJ
    Chung, SS
    Kao, TY
    Shiue, RY
    Wang, CJ
    Peng, YK
    41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2003, : 203 - 207
  • [10] Performance evaluation of ultra-thin gate-oxide CMOS circuits
    Marras, A
    De Munari, I
    Vescovi, D
    Ciampolini, P
    SOLID-STATE ELECTRONICS, 2004, 48 (04) : 551 - 559
12345