Reliability of ultra thin gate oxide CMOS devices: Design perspective

被引：0

作者：

Parthasarathy, C. R. ^{[1
,3
]}

Denais, M. ^{[1
]}

Huard, V. ^{[2
]}

Ribes, G. ^{[1
]}

Vincent, E. ^{[1
]}

Bravaix, A. ^{[3
]}

机构：

[1] STMicroelect, 850,Rue Jean Monet, F-38926 Crolles, France

[2] Philips Semicond, F-38926 Crolles, France

[3] UMR CNRS 6137, Maison Technol, L2MP ISEN, F-83000 Toulon, France

来源：

2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective-in terms of characterization, mechanisms and circuit analysis-introducing assessment of multiple degradation modes on same device.

引用

页码：122 / +

页数：3

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