Process development of electroplate bumping for ULSI flip chip technology

For flip-chip packaging applications, a fine pitch bump process on LSI wafers is required due to increased chip circuit density, operating speed, and performance. Plating process is suitable for making the fine pitch bumps with high-speed deposition and high reliability. At the same time, lead-free processes, for electronic devices and components, are required in several years to address environmental concerns. Also, high-speed bumping processes have to be developed for mass production; low cost, small footprint, and high throughput. Ebara has developed electroplating technologies for eutectic Sn-Pb solder, high lead solder, lead-free solder, and copper stud bumps on silicon wafers with higher deposition rates. The bumps were fabricated as column or mushroom type using resist plating masks, such as negative, positive spin-on, and dry film photo resists. The thickness of photo resist used was in the range of 50mum to 120mum, the diameter of the pattern was in the range of 70mum. to 250mum, and the aspect ratio of resist patterns was in the range of 0.5 to 1.5. Ebara's electroplating processes were carried out using appropriate plating solutions and anodes with high plating rates from 0.5mum/min to 5.5mum/min, depending on the material deposited. The results show that Ebara's processes are suitable for mass production, with well-controlled bump geometry and composition over the entire wafer. In this paper, Ebara will describe the processes and results on bump properties, such as composition, melting point, and microstructure.