Eutectic Sn-Ag solder bump process for ULSI flip chip technology

The novel developed Sn-Ag eutectic solder bump process provides several advantages over conventional solder bump process schemes. Steep wall bumps as plated were fabricated using the nega-type photo resist with a thickness of more than 50 mu m by one time spin coating. This improves productivity for mass production. The 2-step electroplating process was performed using separate plating reactors for Ag and Sn. The eutectic Sn-Ag alloy bumps were easily obtained by annealing the metal stacks with Sn laver on Ag layer sequentially electroplated. This electroplating process does not need to strict control of the content ratio of A.g to Sn in an alloy plating solution even with increasing electroplating depositions. The novel developed process gives the within-wafer uniformity of the bump height as reflowed of less than 10% and of the Sn-Ag alloy composition as reflowed of less than +/-0.5wt.%Ag, analyzed by ICP spectrometry. Shear strength measurements were performed to know thermal stability for the structure of Cu pads/Ti/Ni/Pd/Sn-Ag eutectic solder stack. In the case of the Ti (100nm)/Ni (300nm)/Pd (50nm) barrier metal stacks, the shear strength after 5 times annealing in N2 ambience at 260 degrees C decreased to 70% than that as reflowed. As the Ti becomes thicker in the Ti/Ni/Pd metal stack, shear strengths are improved. Comparing the structure of Cu/Ti/Ni/Pd/Sn-Ag eutectic solder with the case of Ta/Ti/Ni/Pd and Nb/Ti/Ni/Pd barrier metal stacks, the analysis results of Auger spectrometry show that Sn diffusion into Cu to form Cu-Sn alloy was observed only in Cu/Ta/Ti/Ni/Pd barrier metal stacks. These results suggest that the same Ti/Ni/Pd barrier metal stack as used in Sn-Pb solder bump and Au bump is viable for ULSIs with Cu interconnects.