A low cost bumping process for flip chip and CSP applications

Area array packages (flip chip CSP and EGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP- WL) is described in detail. This paper is divided in two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSP 's, In order to achieve large bumps an optimized printing method will be presented Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.