A Fast High-Resolution Time-to-Digital Converter Implemented in a Zynq 7010 SoC

A high-resolution time-to-digital converter (TDC) was implemented on a Red Pitaya board, featuring a Xilinx Zynq 7010 fully programmable 28-nm system on chip (SoC). The TDC is based on an internal tapped delay line for fine time measurements. First experimental results point towards very high performance of the design, achieving 350 MHz clock speed and sub 20 ps time resolution. The work is part of a Master thesis research and serves as a demonstration of what is possible today with a fairly simple design and a low-cost modern FPGA. The chip used is the smallest dual-core Zynq-7000 device, which makes development boards like Red Pitaya easily affordable for universities. We make good use of on-board Linux to send gathered data via Ethernet to a PC client with a graphical user interface to access the TDC. The design is fully customizable and comes in the form of an independent TDC channel IP core. This offers the possibility of easily implementing TDC systems with an arbitrary number of TDC channels.