A high-resolution and fast-conversion time-to-digital converter

被引：0
|
作者：
Hwang, CS [1 ]
Chen, PK [1 ]
Tsao, HW [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resolution. The flash-type operation enables the TDC to resolve the time difference for fine conversion in less than one reference clock cycle. The DNL can be less than +/-0.03LSB and INL less than +/-0.04LSB. We confirm the results based on 0.35um CMOS process technology.
引用
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页码：37 / 40
页数：4
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