High-resolution time-to-digital converter utilising fractional difference conversion scheme

被引：9

作者：

Xing, N. ^{[1
]}

Shin, W. -Y. ^{[1
]}

Jeong, D. -K. ^{[1
]}

Kim, S. ^{[1
]}

机构：

[1] Seoul Natl Univ, Seoul, South Korea

来源：

ELECTRONICS LETTERS | 2010年 / 46卷 / 06期

关键词：

Frequency converters - Delay lock loops;

D O I：

10.1049/el.2010.2698

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-resolution process, voltage and temperature (PVT)-insensitive time-to-digital converter (TDC) is presented, based on a Vernier delay-line, in which the propagation delays in the upper and lower buffer chains are stabilised by two different delay-locked-loops (DLLs). The limitation on its resolution, imposed by DLL jitter and input range of time intervals, is analysed. Simulation results show that the proposed TDC achieves a resolution as high as 22.7 ps while consuming only 2.7 mW.

引用

页码：398 / U32

页数：2

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