A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays

被引：186

作者：

Song, J ^{[1
]}

An, Q ^{[1
]}

Liu, SB ^{[1
]}

机构：

[1] Univ Sci & Technol China, Dept Modern Phys, Fast Elect Lab, Hefei 230026, Peoples R China

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2006年 / 53卷 / 01期

基金：

中国国家自然科学基金;

关键词：

field programmable gate arrays (FPGAs); time-to-digital converter (TDC); time measurement; code density test;

D O I：

10.1109/TNS.2006.869820

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-resolution time-to-digital converter (TDC) implemented in a general purpose field-programmable-gate-array (FPGA) is presented. Dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement. Two Gray-code counters, working on in-phase and out-of-phase system clocks respectively, are designed to get the stable value of the coarse time measurement. The fine time code and the coarse time counter value, along with the channel identifier, are then written into a first-in first-out (FIFO) buffer. Tests have been done to verify the performance of the TDC. The resolution after calibration can reach 50 ps.

引用

页码：236 / 241

页数：6

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