共 50 条
- [1] FPGA implementation of a high-resolution time-to-digital converter [J]. 2007 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-11, 2007, : 504 - 507
- [3] High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip [J]. APPLIED SCIENCES-BASEL, 2017, 7 (01):
- [5] A Fast High-Resolution Time-to-Digital Converter Implemented in a Zynq 7010 SoC [J]. 2019 27TH AUSTROCHIP WORKSHOP ON MICROELECTRONICS (AUSTROCHIP), 2019, : 29 - 34
- [6] High Resolution Time-to-digital Converter for PET Imaging [J]. PROCEEDINGS OF 2020 INTERNATIONAL CONFERENCE ON INNOVATIVE TRENDS IN COMMUNICATION AND COMPUTER ENGINEERING (ITCE), 2020, : 295 - 298
- [8] A Multichannel High-Resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA) [J]. 2011 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (NSS/MIC), 2011, : 876 - 879
- [9] Design of a High-Resolution Time-to-Digital Converter Chip [J]. 2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 921 - 923
- [10] High-resolution and multi-channel time interval counter using time-to-digital converter and FPGA [J]. PROCEEDINGS OF THE 2007 IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM-JOINTLY WITH THE 21ST EUROPEAN FREQUENCY AND TIME FORUM, VOLS 1-4, 2007, : 1324 - 1326