Optimized design of Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches

被引：5

作者：

Sato-Iwanaga, Junko ^{[1
]}

Inoue, Akira ^{[1
]}

Sorada, Haruyuki ^{[1
]}

Takagi, Takeshi ^{[1
]}

Rothschild, Aude ^{[2
]}

Loo, Roger ^{[2
]}

Biesemans, Serge ^{[2
]}

Ito, Choshu ^{[3
]}

Liu, Yang ^{[3
]}

Dutton, Robert W. ^{[3
]}

Tsuchiya, Hideaki ^{[4
]}

机构：

[1] Panasonic Corp, R&D Div, Osaka 5708501, Japan

[2] IMEC, B-3001 Heverlee, Belgium

[3] Stanford Univ, Stanford, CA 94305 USA

[4] Kobe Univ, Nada Ku, Kobe, Hyogo 6578501, Japan

来源：

SOLID-STATE ELECTRONICS | 2014年 / 91卷

关键词：

SiGe; MOS; FET; Semiconductor; Device simulation; PASSIVATION LAYER; ELECTRON-MOBILITY; PERFORMANCE; THICKNESS; GE; ENHANCEMENT; IMPACT;

D O I：

10.1016/j.sse.2013.09.010

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we study the hole transport properties in strained-SiGe channel p-MOSFETs (sSG pMOSFETs) with a Si-cap layer, which is introduced to avoid degradation of interface quality between gate oxide and channel. By using device simulation considering Ge diffusion, quantum confinement effects, surface roughness scattering and Coulomb scattering due to interface charges, and also experimental measurement, we clarify the roles of a Si-cap layer in sSG pMOSFETs, and furthermore propose its optimized design to obtain a higher device performance. We also demonstrate that the insertion of a Si-cap layer is effective to reduce an OFF-state leakage current owing to an increased band gap energy in the Si-cap layer. (C) 2013 Elsevier Ltd. All rights reserved.

引用

页码：1 / 8

页数：8

共 29 条

[1] Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs
Gomez, Leonardo
Hashemi, Pouya
Hoyt, Judy L.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (11) : 2644 - 2651
[2] Hole mobility enhancement in strained-Si/strained-SiGe heterostructure p-MOSFETs fabricated on SiGe-on-insulator (SGOI)
Cheng, ZY
Jung, JW
Lee, ML
Pitera, AJ
Hoyt, JL
Antoniadis, DA
Fitzgerald, EA
[J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2004, 19 (05) : L48 - L51
[3] Study of Strained-Si/SiGe Channel p-MOSFETs Using TCAD
Das, Sanghamitra
Dash, Tara Prasanna
Nanda, Rajib Kumar
Maiti, C. K.
[J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMPUTING & COMMUNICATION SYSTEMS, MCCS 2015, 2018, 453 : 181 - 188
[4] Enhanced Hole Mobility in High Ge Content Asymmetrically Strained-SiGe p-MOSFETs
Gomez, Leonardo
Chleirigh, C. Ni
Hashemi, P.
Hoyt, J. L.
[J]. IEEE ELECTRON DEVICE LETTERS, 2010, 31 (08) : 782 - 784
[5] Strained-Si channel heterojunction p-MOSFETS
Armstrong, GA
Maiti, CK
[J]. SOLID-STATE ELECTRONICS, 1998, 42 (04) : 487 - 498
[6] Hole Velocity Enhancement in Sub-100 nm Gate Length Strained-SiGe Channel p-MOSFETs on Insulator
Gomez, L.
Hashemi, P.
Hoyt, J. L.
[J]. 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2008, : 163 - 164
[7] Optimized Si-cap layer thickness for tensile-strained-Si/compressively strained SiGe dual-channel transistors in 0.13 μm complementary metal oxide semiconductor technology
Wang, YP
Wu, SL
Chang, SJ
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2005, 44 (37-41): : L1248 - L1251
[8] Design and simulation of strained Si/SiGe dual channel MOSFETs
Goyal, Puneet
Moon, James E.
Kurinec, Santosh K.
[J]. 2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2, 2007, : 327 - +
[9] Effects of Si-cap thickness and temperature on device performance of Si/Ge1-xCx/Si p-MOSFETs
Jamil, Mustafa
Liu, En-Shao
Ferdousi, Fahmida
Donnelly, Joseph P.
Tutuc, Emanuel
Banerjee, Sanjay K.
[J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2010, 25 (04)
[10] Reliability predictions for strained-Si/SiGe quantum-well p-MOSFETs
Mahato, S. S.
Maiti, T. K.
Chakraborty, P.
Sarkar, S. K.
Maiti, C. K.
[J]. PROCEEDINGS OF THE 2007 INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES: IWPSD-2007, 2007, : 198 - +

← 1 2 3 →