Effects of Si-cap thickness and temperature on device performance of Si/Ge1-xCx/Si p-MOSFETs

被引：3

作者：

Jamil, Mustafa ^{[1
]}

Liu, En-Shao ^{[1
]}

Ferdousi, Fahmida ^{[1
]}

Donnelly, Joseph P. ^{[1
]}

Tutuc, Emanuel ^{[1
]}

Banerjee, Sanjay K. ^{[1
]}

机构：

[1] Univ Texas Austin, Microelect Res Ctr, Austin, TX 78758 USA

来源：

SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2010年 / 25卷 / 04期

关键词：

GERMANIUM; LAYERS; FIELD; JUNCTIONS; SILICON;

D O I：

10.1088/0268-1242/25/4/045005

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge1-xCx/Si p-MOSFETs. The silicon-cap thickness (3-9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and I-on-I-off ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge1-xCx interface was quantitatively extracted by fitting the stair-case behavior of split C-V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations.

引用

页数：7

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