Mechanical reliability evaluation of chip scale power package

被引:0
|
作者
Ghosh, Kaushik [1 ]
McCluskey, F. Patrick [1 ]
Temple, Victor A. K. [1 ]
机构
[1] Univ Maryland, Dept Mech Engn, CALCE EPSC, College Pk, MD 20742 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
ThinPak (TM) is a highly volumetrically efficient technology for packaging high power semiconductor devices for a wide range of applications. Its elimination of wirebonds lowers thermal and electrical resistivity and impedance, while its two sided solder attach enhances cooling, thus promising improved performance and reliability. In this study, the thermomechanical durability of the ThinPak (TM) module was investigated using physics-of-failure modeling and accelerated thermal cycle testing. Post-test analysis of samples indicated that failure! occurred first in the eutectic solder used to attach the ThinPak (TM) to the DBC substrate. The high lead solder in the ThinPak (TM) itself was very robust against failure. Viscoplastic stress analysis combined with Coffin-Manson damage modeling was used to quantify creep-fatigue accumulation. The failure criterion of a 20% increase in forward voltage drop was used in conjunction with stress analysis to assess the time to failure at the DBC/ThinPak (TM) interface. The calibrated constants for the fatigue ductility and exponent were then used to assess the life of the assembly for different temperature loading conditions.
引用
收藏
页码:77 / 85
页数:9
相关论文
共 50 条
  • [41] Thermal-mechanical coupling analysis for coupled power and thermal cycling reliability of chip-scale packages
    Lai, YS
    Wang, TH
    Lee, CC
    THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS, 2005, : 539 - 544
  • [42] Thermal-Mechanical Simulation and Analysis on Structural Caused Package Induced Stress in Stacked Chip Scale Package
    钱峰
    程秀兰
    刘恩峰
    上海交通大学学报, 2007, (S2) : 139 - 143
  • [43] Reliability Consequences of the Chip-Package Interactions
    van Driel, W. D.
    2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 406 - 411
  • [44] Thermal-mechanical simulation and analysis on structural caused package induced stress in stacked chip scale package
    School of Microelectronic, Shanghai Jiaotong Univ., Shanghai 200030, China
    Shanghai Jiaotong Daxue Xuebao, 2007, SUPPL. (139-143): : 139 - 143
  • [45] Investigation of interconnect design on Chip package interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip chip package
    Uchibori, Chihiro J.
    Zhang, Xuefeng
    Ho, Paul S.
    Nakamura, Tomoji
    PROCEEDINGS OF THE IEEE 2008 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2008, : 150 - 152
  • [46] Vibrational fatigue and reliability of package-on-package stacked chip assembly
    Yang, Bing
    Li, Dongbo
    Yang, Haiying
    Hu, Yongle
    Yang, Ping
    MICROELECTRONICS JOURNAL, 2019, 92
  • [47] Mechanical reliability modeling and characterization for Package-On-Package
    Amagai, Masazumi
    Suzuki, Yutaka
    Abe, Kenji
    Kim, YoungBae
    Sano, Hitoyuki
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1445 - 1452
  • [48] Evaluation of solder joint reliability in flip chip package under thermal shock test
    Kim, DG
    Kim, JW
    Jung, SB
    THIN SOLID FILMS, 2006, 504 (1-2) : 426 - 430
  • [49] Technical evaluation of a near chip scale size Flip Chip Plastic Ball Grid Array package
    Jimarez, M
    Li, L
    Tytran, C
    Loveland, C
    Obrzut, J
    48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 495 - 502
  • [50] Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder
    Zhang Xueren
    Zhu Wenhui
    Edith, Poh
    Boon, Tan Hien
    EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 1096 - 1101