共 50 条
- [21] Effect of UBM and BCB Layers on the Thermo-Mechanical Reliability of Wafer Level Chip Scale Package (WLCSP) IMPACT: 2009 4TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, 2009, : 361 - 364
- [22] Chip Scale Package with Low Cost Substrate Evaluation and Characterization 2014 IEEE 16TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2014, : 421 - 425
- [24] Board level reliability of various stacked die chip scale package configurations 2003 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 2003, 5288 : 894 - 899
- [25] Analysis of interconnection reliability of dielectric layer for wafer level chip scale package 2015 10TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2015, : 344 - 347
- [27] Influences of packaging materials on the solder joint reliability of chip scale package assemblies INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES AND INTERFACES, PROCEEDINGS, 1999, : 144 - 149
- [28] Robust Power Package Development with Mechanical Simulation and Reliability Validation 2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT), 2012,
- [30] Vibration reliability in flip chip package ADVANCES IN FRACTURE AND STRENGTH, PTS 1- 4, 2005, 297-300 : 899 - 904