Mechanical reliability evaluation of chip scale power package

被引:0
|
作者
Ghosh, Kaushik [1 ]
McCluskey, F. Patrick [1 ]
Temple, Victor A. K. [1 ]
机构
[1] Univ Maryland, Dept Mech Engn, CALCE EPSC, College Pk, MD 20742 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
ThinPak (TM) is a highly volumetrically efficient technology for packaging high power semiconductor devices for a wide range of applications. Its elimination of wirebonds lowers thermal and electrical resistivity and impedance, while its two sided solder attach enhances cooling, thus promising improved performance and reliability. In this study, the thermomechanical durability of the ThinPak (TM) module was investigated using physics-of-failure modeling and accelerated thermal cycle testing. Post-test analysis of samples indicated that failure! occurred first in the eutectic solder used to attach the ThinPak (TM) to the DBC substrate. The high lead solder in the ThinPak (TM) itself was very robust against failure. Viscoplastic stress analysis combined with Coffin-Manson damage modeling was used to quantify creep-fatigue accumulation. The failure criterion of a 20% increase in forward voltage drop was used in conjunction with stress analysis to assess the time to failure at the DBC/ThinPak (TM) interface. The calibrated constants for the fatigue ductility and exponent were then used to assess the life of the assembly for different temperature loading conditions.
引用
收藏
页码:77 / 85
页数:9
相关论文
共 50 条
  • [21] Effect of UBM and BCB Layers on the Thermo-Mechanical Reliability of Wafer Level Chip Scale Package (WLCSP)
    Chan, Y. S.
    Lee, S. W. Ricky
    Song, F.
    Lo, C. C. Jeffery
    Jiang, T.
    IMPACT: 2009 4TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, 2009, : 361 - 364
  • [22] Chip Scale Package with Low Cost Substrate Evaluation and Characterization
    Lin, Vito
    Lin, Vincent
    Kao, Nicholas
    Jiang, Don Son
    Hsiao, C. S.
    2014 IEEE 16TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2014, : 421 - 425
  • [23] Modular sensor chip design for package stress evaluation and reliability characterisation
    Trigg, A. D.
    Chong, Chai Tai
    Zhang Xiaowu
    Tong, Chen Xian
    Ching, Wai Leong
    MICROELECTRONICS RELIABILITY, 2012, 52 (08) : 1581 - 1585
  • [24] Board level reliability of various stacked die chip scale package configurations
    Carson, F
    Zahn, B
    Mitchell, D
    2003 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 2003, 5288 : 894 - 899
  • [25] Analysis of interconnection reliability of dielectric layer for wafer level chip scale package
    Wang, Chiyu
    Hsieh, Adren
    Wang, Yaochen
    Pai, Archer
    Pan, Cheng-Tang
    Wang, Shao-Yu
    Chiu, Chen-Chih
    Wang, Bo-Sheng
    Yang, Tsung-Lin
    2015 10TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2015, : 344 - 347
  • [26] Dynamic reliability approach of chip scale package assembly under vibration environment
    Yang, Ping
    Tang, Xiusheng
    Liu, Yu
    Wang, Shuting
    Yang, Jianming
    MICROELECTRONICS INTERNATIONAL, 2014, 31 (02) : 71 - 77
  • [27] Influences of packaging materials on the solder joint reliability of chip scale package assemblies
    Wilde, J
    Cheng, ZN
    Wang, GZ
    INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES AND INTERFACES, PROCEEDINGS, 1999, : 144 - 149
  • [28] Robust Power Package Development with Mechanical Simulation and Reliability Validation
    Zhang, Xueren
    Goh, Kim-yong
    Ma, Yiyi
    Wong, Wingshenq
    2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT), 2012,
  • [29] Chip scale package issues
    Ghaffarian, R
    MICROELECTRONICS RELIABILITY, 2000, 40 (07) : 1157 - 1161
  • [30] Vibration reliability in flip chip package
    Yeh, MK
    Zhong, WX
    ADVANCES IN FRACTURE AND STRENGTH, PTS 1- 4, 2005, 297-300 : 899 - 904