Thermal-mechanical coupling analysis for coupled power and thermal cycling reliability of chip-scale packages

被引：0

作者：

Lai, YS ^{[1
]}

Wang, TH ^{[1
]}

Lee, CC ^{[1
]}

机构：

[1] Adv Semicond Engn Inc, Stress Reliabil Lab, Kaohsiung, Taiwan

来源：

THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is carried out in this paper to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array chip-scale packages under coupled power and thermal cycling test conditions. Pure thermal cycling and pure power cycling test conditions are also examined and compared.

引用

页码：539 / 544

页数：6

共 50 条

[1] Thermal-mechanical coupling analysis of board-level chip-scale packages subjected to power cycling of different powering durations
Wang, Tong Hong
Lee, Chang-Chi
Lai, Yi-Shao
Lee, Kuo-Yuan
PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION 2007, VOL 5: ELECTRONICS AND PHOTONICS, 2008, : 241 - 246
[2] Effect of power cycling duration on coupled power and thermal cycling reliability of board-level chip-scale packages
Wang, TH
Lai, YS
Lee, CC
PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 119 - 124
[3] Thermal-mechanical coupling analysis for coupled power- and thermal-cycling reliability of board-level electronic packages
Lai, Yi-Shao
Wang, Tong Hong
Lee, Chang-Chi
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2008, 8 (01) : 122 - 128
[4] Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditions
Wang, Tong Hong
Lai, Yi-Shao
Lin, Yu-Cheng
MICROELECTRONICS RELIABILITY, 2008, 48 (01) : 132 - 139
[5] Transient thermal analysis for board-level chip-scale packages subjected to coupled power and thermal cycling test conditions
Wang, Tong Hong
Lee, Chang-Chi
Lai, Yi-Shao
Lin, Yu-Cheng
JOURNAL OF ELECTRONIC PACKAGING, 2006, 128 (03) : 281 - 284
[6] Correlation between power cycling and thermal cycling fatigue reliabilities of chip-scale packages
Wang, TH
Lee, CC
Lai, YS
Huang, CE
29TH INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 2004, : 26 - 30
[7] Influence of Power Cycling Durations on Thermal and Fatigue Reliability Characteristics of Board-Level Chip-Scale Packages
Wang, Tong Hong
Lee, Chang-Chi
Lai, Yi-Shao
Lee, Kuo-Yuan
JOURNAL OF ELECTRONIC PACKAGING, 2009, 131 (01) : 0110011 - 0110015
[8] Analysis and modeling verification for thermal-mechanical deformation in flip-chip packages
Zhao, JH
Dai, X
Ho, PS
48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 336 - 344
[9] Coupled power and thermal cycling characteristics and reliability of stacked-die packages
Wang, Tong Hong
Lee, Chang-Chi
Lai, Yi-Shao
Wang, Ching-Chun
2007 INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 202 - 206
[10] Coupled thermal-mechanical simulation methodology to estimate BGA reliability of 2.5D Packages
Nayini, Manish
Horn, Timothy
Patel, Janak
Burrell, Lloyd
2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), 2020, : 1653 - 1658

← 1 2 3 4 5 →