Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditions

被引:3
|
作者
Wang, Tong Hong [1 ,2 ]
Lai, Yi-Shao [2 ]
Lin, Yu-Cheng [1 ]
机构
[1] Natl Cheng Kung Univ, Dept Engn Sci, Tainan 70101, Taiwan
[2] Adv Semicond Engn Inc, Cent Labs, Kaohsiung 811, Taiwan
关键词
D O I
10.1016/j.microrel.2007.02.011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic packages, a coupled power and thermal cycling test has been proposed. In this study, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array chip-scale packages under coupled power and thermal cycling test conditions. Effects of different power cycling durations are studied. A pure thermal cycling condition is also examined and compared. Numerical results indicate that, for the coupled power and thermal cycling test, a shorter power cycling duration in general leads to a shorter fatigue life. However, the temperature compensation effect elongates the fatigue life under certain power cycling durations. (c) 2007 Published by Elsevier Ltd.
引用
收藏
页码:132 / 139
页数:8
相关论文
共 50 条
  • [1] Effect of power cycling duration on coupled power and thermal cycling reliability of board-level chip-scale packages
    Wang, TH
    Lai, YS
    Lee, CC
    PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 119 - 124
  • [2] Transient thermal analysis for board-level chip-scale packages subjected to coupled power and thermal cycling test conditions
    Wang, Tong Hong
    Lee, Chang-Chi
    Lai, Yi-Shao
    Lin, Yu-Cheng
    JOURNAL OF ELECTRONIC PACKAGING, 2006, 128 (03) : 281 - 284
  • [3] Influence of Power Cycling Durations on Thermal and Fatigue Reliability Characteristics of Board-Level Chip-Scale Packages
    Wang, Tong Hong
    Lee, Chang-Chi
    Lai, Yi-Shao
    Lee, Kuo-Yuan
    JOURNAL OF ELECTRONIC PACKAGING, 2009, 131 (01) : 0110011 - 0110015
  • [4] Effects of different drop test conditions on board-level reliability of chip-scale packages
    Lai, Yi-Shao
    Yang, Po-Chuan
    Yeh, Chang-Lin
    MICROELECTRONICS RELIABILITY, 2008, 48 (02) : 274 - 281
  • [5] Prediction of board-level reliability of chip-scale packages under consecutive drops
    Yeh, CL
    Lai, YS
    Kao, CL
    PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 73 - 80
  • [6] Investigations of board-level drop reliability of wafer-level chip-scale packages
    Lai, Yi-Shao
    Yeh, Chang-Lin
    Wang, Ching-Chun
    JOURNAL OF ELECTRONIC PACKAGING, 2007, 129 (01) : 105 - 108
  • [7] A numerical study of board-level stacked-die packages under coupled power and thermal cycling test conditions
    Wang, Tong Hong
    Lee, Chang-Chi
    Wang, Ching-Chun
    Lai, Yi-Shao
    2006 INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY CONFERENCE TAIWAN (IMPACT), PROCEEDINGS, 2006, : 123 - +
  • [8] Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition
    Lai, YS
    Yang, PF
    Yeh, CL
    MICROELECTRONICS RELIABILITY, 2006, 46 (2-4) : 645 - 650
  • [9] Thermal-mechanical coupling analysis of board-level chip-scale packages subjected to power cycling of different powering durations
    Wang, Tong Hong
    Lee, Chang-Chi
    Lai, Yi-Shao
    Lee, Kuo-Yuan
    PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION 2007, VOL 5: ELECTRONICS AND PHOTONICS, 2008, : 241 - 246
  • [10] Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions
    Shih, Meng-Kai
    Liu, Yu-Hao
    Lee, Calvin
    Hung, C. P.
    MATERIALS, 2023, 16 (12)