Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditions

被引:3
|
作者
Wang, Tong Hong [1 ,2 ]
Lai, Yi-Shao [2 ]
Lin, Yu-Cheng [1 ]
机构
[1] Natl Cheng Kung Univ, Dept Engn Sci, Tainan 70101, Taiwan
[2] Adv Semicond Engn Inc, Cent Labs, Kaohsiung 811, Taiwan
关键词
D O I
10.1016/j.microrel.2007.02.011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic packages, a coupled power and thermal cycling test has been proposed. In this study, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array chip-scale packages under coupled power and thermal cycling test conditions. Effects of different power cycling durations are studied. A pure thermal cycling condition is also examined and compared. Numerical results indicate that, for the coupled power and thermal cycling test, a shorter power cycling duration in general leads to a shorter fatigue life. However, the temperature compensation effect elongates the fatigue life under certain power cycling durations. (c) 2007 Published by Elsevier Ltd.
引用
收藏
页码:132 / 139
页数:8
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