A novel VLSI architecture for clustering analysis

被引：0
|
作者：
Lai, MF
Hsieh, CH
机构：
来源：
APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96 | 1996年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a novel VLSI architecture for the squared-error clustering algorithm The proposed architecture reduces the huge number of processing elements (PEs) required by the other previous architectures. The system uses only local communication between adjacent PES and if is modular, regular,and expandable. The VLSI implementation of high speed clustering analysis can be realized with significantly less circuit complexity based on the proposed architecture.
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收藏
页码：484 / 487
页数：4
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