A Novel VLSI Architecture for Euclid Algorithm

The Reed-Solomon (RS) coding is the most powerful and standardized technique for error and coding correction. Because of this excellent capability for correcting burst errors, it has been widely used for digital communication systems. In this paper a novel architecture of improved Euclid Algorithm for RS decoding is presented. This architecture implements the time domain algorithm with least complex circuitry and significant reduction in silicon area. The most important saving in the proposed architecture is in the number of Galois Field (GF) multipliers, the most area and power consuming component. Earlier architectures are using more number of GF multipliers, but in the proposed architecture the number of GF multipliers has been drastically reduced to unity. This makes the VLSI implementation of the architecture more easy and area and power efficient. Besides, microprogramming approach has been proposed for the control design, which makes it more flexible.