A 6-bit 220-MS/s Time-Interleaving SAR ADC in 0.18-μm Digital CMOS Process

被引：8

作者：

Liu, Chun-Cheng ^{[1
]}

Huang, Yi-Ting ^{[1
]}

Huang, Guan-Ying ^{[1
]}

Chang, Soon-Jyh ^{[1
]}

Huang, Chung-Ming ^{[2
]}

Huang, Chih-Haur ^{[2
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, 1 Univ Rd, Tainan 70101, Taiwan

[2] Himax Technol Inc, Tainan, Taiwan

来源：

2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | 2009年

关键词：

D O I：

10.1109/VDAT.2009.5158133

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-mu m 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm(2) active area.

引用

页码：215 / +

页数：2

共 50 条

[21] Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS
Konwar, Shruti
Roy, Harshit
Chiang, Shiuh-Hua Wood
Sahoo, Bibhu Datta
IEEE SOLID-STATE CIRCUITS LETTERS, 2022, 5 : 243 - 246
[22] A 10-bit Asynchronous SAR ADC with Scalable Conversion Time in 0.18μm CMOS
Tung, Po-Chiang
Fan, Duen-Ting
Tsai, Tsung-Heng
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1454 - 1457
[23] A 6-GS/s 6-bit Time Interleaved SAR-ADC
Huang, Hao
Groezing, Markus
Digel, Johannes
Ferenci, Damir
Lang, Felix
Berroth, Manfred
2013 8TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2013, : 37 - 40
[24] MDAC Design for an 8-bit 40 MS/s Pipelined ADC in a 0.18μm CMOS Process
Dendouga, Abdelghani
Oussalah, Slimane
Lakhdar, Nacereddine
Lakehal, Brahim
2018 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRICAL ENGINEERING (ICCEE), 2018, : 160 - 162
[25] A 42 mW 2 GS/s 4-bit flash ADC in 0.18-μm CMOS
Wu, Lianhong
Huang, Fengyi
Gao, Yang
Wang, Yan
Cheng, Jia
2009 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS AND SIGNAL PROCESSING (WCSP 2009), 2009, : 1455 - 1459
[26] A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology附视频
乔宁
张国全
杨波
刘忠立
于芳
半导体学报, 2012, (09) : 115 - 123
[27] A Design of 6-bit125-MS/s SAR ADC in 0.13-μm MM/RF CMOS Process
Rajasekar, R.
Ramakrishna, P. V.
2012 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED 2012), 2012, : 23 - 27
[28] A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 mu m CMOS
Li Dong
Meng Qiao
Li Fei
JOURNAL OF SEMICONDUCTORS, 2016, 37 (01)
[29] A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
Chen, Shuo-Wei Michael
Brodersen, Robert W.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) : 2669 - 2680
[30] A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration
Huang, Chun-Cheng
Wang, Chung-Yi
Wu, Jieh-Tsorng
2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010, : 159 - +

← 1 2 3 4 5 →