A 6-bit 220-MS/s Time-Interleaving SAR ADC in 0.18-μm Digital CMOS Process

被引：8

作者：

Liu, Chun-Cheng ^{[1
]}

Huang, Yi-Ting ^{[1
]}

Huang, Guan-Ying ^{[1
]}

Chang, Soon-Jyh ^{[1
]}

Huang, Chung-Ming ^{[2
]}

Huang, Chih-Haur ^{[2
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, 1 Univ Rd, Tainan 70101, Taiwan

[2] Himax Technol Inc, Tainan, Taiwan

来源：

2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | 2009年

关键词：

D O I：

10.1109/VDAT.2009.5158133

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-mu m 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm(2) active area.

引用

页码：215 / +

页数：2

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