Error Recovery of Low Resistance State in 40nm TaOx-based ReRAM

被引：0
|
作者：
Maeda, Kazuki [1 ]
Fukuyama, Shouhei [1 ]
Takeuchi, Ken [1 ]
Yasuhara, Ryutaro [2 ]
Mishima, Satoshi [2 ]
机构：
[1] Chuo Univ, Dept Elect Elect & Commun Engn, Tokyo, Japan
[2] Panasonic Semicond Solut Co Ltd, 1 Kotari Yakemachi, Kyoto 6178520, Japan
来源：
2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2017年
关键词：
ReRAM; endurance; error recovery;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Error recovery effect of low resistance state (LRS) has been observed for the first time in set/reset cycling endurance in 40nm TaOx-based ReRAM cell. LRS error cells, which have an abnormally high resistance, are recovered to normal LRS by the relaxation time for error recovery between set and reset. This phenomenon can be explained by oxygen vacancy (V-O) diffusion from TaOx layer to reconstruct the conductive filament in error cells. Based on this phenomenon, the bit error rate (BER) in ReRAM for the future high speed storage system is reduced by the dispersed data writing with the wear-leveling.
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页数：6
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