Off State Incorporation into the 3 energy mode Device Lifetime Modeling for advanced 40nm CMOS node

被引：20

作者：

Bravaix, A. ^{[1
]}

Guerin, C. ^{[1
,3
]}

Goguenheim, D. ^{[1
]}

Huard, V. ^{[2
]}

Roy, D. ^{[2
]}

Besset, C. ^{[2
]}

Renard, S. ^{[2
]}

Randriamihaja, Y. Mamy ^{[2
]}

Vincent, E. ^{[2
]}

机构：

[1] Maison Technol, UMR CNRS 6242, ISEN IM2NP, Pl G Pompidou, F-83000 Toulon, France

[2] Crolles Alliance 2, STMicroelect, F-38926 Crolles, France

[3] Roth & Rau Switzerland AG, CH-2000 Neuchatel, Switzerland

来源：

2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年

关键词：

Off Mode; Gate-Induced Drain Leakage; Cold Carriers; Band to Band Tunneling; Hot Carriers; Interface traps; Oxide traps; Multi Vibrational Excitation; High Temperature; HOT-CARRIER DEGRADATION; NBTI DEGRADATION; LEAKAGE CURRENT; INTERFACE; REDUCTION; GATE; MECHANISMS; TRANSISTOR; GENERATION; MOSFETS;

D O I：

10.1109/IRPS.2010.5488852

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-VT regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.

引用

页码：55 / 64

页数：10

共 3 条

[1] Packaging Induced Stress Effects Investigations on 40nm CMOS Technology Node : Measurements and Optimization of Device Shifts
Ewuame, Komi Atchou
Bouchard, Pierre-Olivie
Fiori, Vincent
Gallois-Garreignot, Sebastien
Inal, Karim
Tavernier, Clement
[J]. 2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC), 2015,
[2] Hot-Carrier to Cold-Carrier Device Lifetime Modeling with Temperature for Low power 40nm Si-Bulk NMOS and PMOS FETs
Bravaix, A.
Huard, V.
Goguenheim, D.
Vincent, E.
[J]. 2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
[3] Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device
Ryu, Donghyun
Myeong, Ilho
Lee, Jang Kyu
Kang, Myounggon
Jeon, Jongwook
Shin, Hyungcheol
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (06) : 2532 - 2537

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