Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process

The building block computing system can build various systems by connecting small-sized chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). First, we have developed TCI IP by using the Renesas 65nm SOTB process and verified it with a simple TEG chip. Then several family chips have been developed with the IP; Geyser-TT (MIPS R3000 compatible processor), SNACC (neural network accelerator), CC-SOTB2 (improved CGRA), KVS (the accelerator for Key-Value-Store database), and SMTT (Shared Memory for Twin Tower). All of these chips worked alone without problems. However, when these chips were stacked to construct a system, problems were found on some combination of chips that TCI did not operate as designed. In order to investigate the cause of the trouble, we have developed a sophisticated tester chip called the TCI Tester. It provides three modes: RAW mode in which handshake lines can be directly controlled, CUBE mode in which the TCI Tester can write the data into the stacked target chips, and LOOP mode which allows continuous write and read operation for a long time working test. Through the evaluation by using a two-TCI Tester stacking system, the following appeared. (1) The maximum transfer frequency of the TCI IP is much lower than 50MHz which is the target value. Only 14MHz for the downward and 9MHz for the upward. (2) The performance of the upward transfer is lower than that of the downward. The poor upward data transfer performance comes from that the voltage drop on the power grid becomes large because of the location of the upward transmitter coil. We can improve it by increasing the number of power pads for the transmitter and enhancing the power grid. However, with the low transfer frequency, the TCI IP worked more than a day continuously.