A controllable low-power dual-port embedded SRAM for DSP processor

被引：0

作者：

Yang, Hao-, I ^{[1
]}

Chang, Ming-Hung ^{[1
]}

Lin, Tay-Jyi ^{[1
]}

Ou, Shih-Hao ^{[1
]}

Deng, Siang-Sen ^{[1
]}

Liu, Chih-Wei ^{[1
]}

Hwang, Wei ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Microelect & Informat Syst Res Ctr, Dept Elect Engn, Hsinchu 300, Taiwan

来源：

MTTD 2007 TAIPEI: PROCEEDINGS OF 2007 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING (MTD '07) | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A codesign of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable precharged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

引用

页码：27 / +

页数：2

共 50 条

[1] Low-power dual-port asynchronous CMOS SRAM design techniques
Soon-Hwei, Tan
Poh-Yee, Loh
Sulaiman, Mohd-Shahiman
Yusoff, Zubaida
INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2007, 37 (02): : 87 - 93
[2] Low power dual-port CMOS SRAM macro design
Microelectronics Center, Sch. of Elec. and Electron. Eng., Nanyang Technological University, Singapore 639798, Singapore
Electron Lett, 15 (1354-1356):
[3] Low power dual-port CMOS SRAM macro design
Wang, H
Liu, PC
Lau, KT
ELECTRONICS LETTERS, 1996, 32 (15) : 1354 - 1356
[4] Embedded power supply for low-power DSP
Gutnik, V
Chandrakasan, AP
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1997, 5 (04) : 425 - 435
[5] Dual-port SDRAM Architecture for Low-power Communication of Internet-of-things Devices
Kim, Sungchan
Yang, Hoeseok
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17 (06) : 893 - 903
[6] A low-power embedded SRAM for wireless applications
Cosemans, Stefan
Dehaene, Wim
Catthoor, Francky
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (07) : 1607 - 1617
[7] DUAL-PORT RAMS SIMPLIFY PROCESSOR COMMUNICATIONS
WYLAND, DC
MICROPROCESSORS AND MICROSYSTEMS, 1988, 12 (10) : 585 - 594
[8] 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning
Mori, Haruki
Izumi, Shintaro
Kawaguchi, Hiroshi
Yoshimoto, Masahiko
2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2018, : 161 - 164
[9] Simulation in low-power embedded processor design
Yoshida, Y
Onoye, T
Shirakawa, I
Kubo, N
SIMULATION IN INDUSTRY: 9TH EUROPEAN SIMULATION SYMPOSIUM 1997, 1997, : 557 - 561
[10] Low-power consumption architecture for embedded processor
Yoshida, Y
Song, BY
Okuhata, H
Onoye, T
Shirakawa, I
1996 2ND INTERNATIONAL CONFERENCE ON ASIC, PROCEEDINGS, 1996, : 77 - 80

← 1 2 3 4 5 →