A controllable low-power dual-port embedded SRAM for DSP processor

被引：0

作者：

Yang, Hao-, I ^{[1
]}

Chang, Ming-Hung ^{[1
]}

Lin, Tay-Jyi ^{[1
]}

Ou, Shih-Hao ^{[1
]}

Deng, Siang-Sen ^{[1
]}

Liu, Chih-Wei ^{[1
]}

Hwang, Wei ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Microelect & Informat Syst Res Ctr, Dept Elect Engn, Hsinchu 300, Taiwan

来源：

MTTD 2007 TAIPEI: PROCEEDINGS OF 2007 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING (MTD '07) | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A codesign of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable precharged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

引用

页码：27 / +

页数：2

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