TFET/CMOS Hybrid Pseudo Dual-Port SRAM for Scratchpad Applications

被引：0

作者：

Gupta, N. ^{[1
]}

Makosiej, A. ^{[2
]}

Thomas, O. ^{[2
]}

Amara, A. ^{[1
]}

Vladimirescu, A. ^{[1
]}

Anghel, C. ^{[1
]}

机构：

[1] ISEP, Paris, France

[2] CEA LETI, Grenoble, France

来源：

2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS) | 2015年

关键词：

Tunneling FET (TFET); SRAM cell; half-selection(HS); write-disturb(WD); SNM; Low STandby Power(LSTP); Dynamic voltage frequency scaling(DVFS);

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A hybrid TFET/CMOS pseudo Dual-Port SRAM (DPSRAM) for embedded scratchpad applications is presented in this paper. The DPSRAM bit cell is designed using sub-32nm TFETs to minimize leakage and the periphery logic is designed in 28-nm FDSOI CMOS to minimize area at a high operating speed. The bit cell is sized under dynamic stability and static noise margin constraints down to 0.6V. The static noise margin analysis is performed in order to be able to support dynamic voltage-frequency scaling (DVFS). The designed DPSRAM has ultra low leakage current less than 5fA/bit and sufficient read/write stability margin larger than 80 mV at 0.6V. For voltages below 1V write-assist techniques are used.

引用

页码：209 / 212

页数：4

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