Test generation for primitive path delay faults in combinational circuits

被引:0
|
作者
Tekumalla, RC
Menon, PR
机构
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a method of identifying primitive path-delay faults in combinational circuits, and deriving robust tests for all robustly testable primitive faults, It uses the concept of sensitizing cubes Pa reduce the search space. This approach helps identify faults that cannot be part of any primitive fault, and avoids attempting test generation for then. Sensitization conditions determined for primitive fault identification are also used in test generation, reducing rest generation effort. Experimental results an some of the ISCAS'85 and MCNC'91 benchmark circuits indicate that they contain a fair number of primitive multiple path delay faults which must be tested.
引用
收藏
页码:636 / 641
页数:6
相关论文
共 50 条
  • [31] A fuzzy test generation algorithm for combinational circuits
    Liu, XD
    Zhang, YG
    Sun, SH
    [J]. ISTM/2003: 5TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1-6, CONFERENCE PROCEEDINGS, 2003, : 1129 - 1130
  • [32] New approach to test generation for combinational circuits
    Zhao, Chun-Hui
    Hou, Yan-Li
    Hu, Jia-Wei
    Lan, Hai-Yan
    [J]. Journal of Harbin Institute of Technology (New Series), 2009, 16 (01) : 61 - 65
  • [33] A new approach to test generation for combinational circuits
    赵春晖
    侯艳丽
    胡佳伟
    兰海燕
    [J]. Journal of Harbin Institute of Technology(New series), 2009, (01) : 61 - 65
  • [34] Simulation and generation of IDDQ tests for bridging faults in combinational circuits
    Chakravarty, S
    Thadikaran, PJ
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (10) : 1131 - 1140
  • [35] An Effective Test Generation Algorithm for Combinational Circuits
    王建潮
    魏道政
    [J]. Journal of Computer Science & Technology, 1986, (04) : 1 - 16
  • [36] Detection of faults in combinational circuits by a self-dual test
    Gessel, M
    Dmitriev, AV
    Sapozhnikov, VV
    Sapozhnikov, VA
    [J]. AUTOMATION AND REMOTE CONTROL, 2000, 61 (07) : 1192 - 1200
  • [37] A method of generating tests for marginal delays and delay faults in combinational circuits
    Takahashi, H
    Matsunaga, T
    Boateng, KO
    Takamatsu, Y
    [J]. SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 320 - 325
  • [38] Diagnosis of single gate delay faults in combinational circuits using delay fault simulation
    Takahashi, H
    Boateng, KO
    Takamatsu, S
    [J]. SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 108 - 112
  • [39] Self-Test Library Generation for In-Field Test of Path Delay Faults
    Anghel, Lorena
    Cantoro, Riccardo
    Masante, Riccardo
    Portolan, Michele
    Sartoni, Sandro
    Reorda, Matteo Sonza
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (11) : 4246 - 4259
  • [40] A method of test generation for path delay faults using stuck-at fault test generation algorithms
    Ohtake, S
    Ohtani, K
    Fujiwara, H
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 310 - 315