A new approach to test generation for combinational circuits

被引:0
|
作者
赵春晖 [1 ]
侯艳丽 [1 ]
胡佳伟 [1 ]
兰海燕 [1 ]
机构
[1] School of Information and Communication Engineering,Harbin Engineering University
关键词
test generation; combinational circuits; particle swarm optimization; chaotic optimization;
D O I
暂无
中图分类号
TN407 [测试和检验];
学科分类号
080903 ; 1401 ;
摘要
Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits (CC) based on the chaotic particle swarm optimization (CPSO) algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS’85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected faults with original test vector and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective.
引用
收藏
页码:61 / 65
页数:5
相关论文
共 50 条
  • [1] New approach to test generation for combinational circuits
    Zhao, Chun-Hui
    Hou, Yan-Li
    Hu, Jia-Wei
    Lan, Hai-Yan
    [J]. Journal of Harbin Institute of Technology (New Series), 2009, 16 (01) : 61 - 65
  • [2] A new approach to test generation for combinational circuits
    赵春晖
    侯艳丽
    胡佳伟
    兰海燕
    [J]. Journal of Harbin Institute of Technology, 2009, 16 (01) : 61 - 65
  • [3] A new test generation algorithm for combinational logic circuits
    Liu, XD
    Sun, SH
    [J]. ISTM/2001: 4TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1 AND 2, CONFERENCE PROCEEDINGS, 2001, : 953 - 957
  • [4] Test pattern generation for combinational circuits
    [J]. Jisuanji Xuebao, 10 (788-793):
  • [5] A new class of sequential circuits with combinational test generation complexity
    Fujiwara, H
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (09) : 895 - 905
  • [6] REALISTIC APPROACH TO DETECTION TEST SET GENERATION FOR COMBINATIONAL LOGIC CIRCUITS
    BENNETTS, RG
    [J]. COMPUTER JOURNAL, 1972, 15 (03): : 238 - +
  • [7] A fuzzy test generation algorithm for combinational circuits
    Liu, XD
    Zhang, YG
    Sun, SH
    [J]. ISTM/2003: 5TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1-6, CONFERENCE PROCEEDINGS, 2003, : 1129 - 1130
  • [8] An Effective Test Generation Algorithm for Combinational Circuits
    王建潮
    魏道政
    [J]. Journal of Computer Science & Technology, 1986, (04) : 1 - 16
  • [9] Forecasting the efficiency of test generation algorithms for combinational circuits
    Xu, SY
    Frank, TJ
    [J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2000, 15 (04) : 326 - 337