A method of test generation for path delay faults using stuck-at fault test generation algorithms

被引:0
|
作者
Ohtake, S [1 ]
Ohtani, K [1 ]
Fujiwara, H [1 ]
机构
[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Ikoma, Nara 6300192, Japan
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a test generation method for non-robust path delay faults using stuck-at fault test generation algorithms. In our method, we first transform an original combinational circuit into a circuit called a partial leaf-dag using path-leaf transformation. Then we generate test patterns using a stuck-at fault test generation algorithm for stuck-at faults in the partial leaf-dag. Finally we transform the test patterns into two-pattern tests for path delay faults in the original circuit. We prove the correctness of the approach and experimental results on several benchmark circuits show the effectiveness of it.
引用
收藏
页码:310 / 315
页数:6
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