Low power commutator for pipelined FFT processors

This paper proposes a low power commutator architecture for the implementation of radix-4 based pipelined Fast Fourier Transform processor. The architecture is based on dual port RAM blocks and exploits the interconnection topology among these blocks for low power implementation. The paper presents the commutator architecture, describes the design methodology and evaluation environment, and provides implementation results showing that the new commutator achieves up to 58% power saving for 256-point and 128-point FFTs as compared to previous commutator architectures.