A pipelined shared-memory architecture for FFT processors

被引：0

作者：

Jia, LH ^{[1
]}

Gao, YH ^{[1
]}

Tenhunen, H ^{[1
]}

机构：

[1] Royal Inst Technol, ESDLab, SE-16440 Stockholm, Sweden

来源：

42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presented a VLSI-architecture for the FFT processors-which locally employed the pipelined architecture to realize the high speed radix-r Process Elements (PEs) and globally utilized the high-radix shared-memory architecture to implement the area-efficient FFT processors Based on this architecture, a high performance 512-point FFT processor has been designed in the 0.6um 3.3v CMOS process to demonstrated its feasibility.

引用

页码：804 / 807

页数：4

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