Scalable FFT processors and pipelined butterfly units

被引：0
|
作者：
Takala, J [1 ]
Punkka, K [1 ]
机构：
[1] Tampere Univ Technol, FIN-33101 Tampere, Finland
来源：
COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION | 2004年 / 3133卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper considers partial-column radix-2 FFT processors. The efficiency of processors based on bit-parallel multipliers, distributed arithmetic, and CORDIC is analyzed with the aid of logic synthesis.
引用
收藏
页码：373 / 382
页数：10
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