The hardware structure design of perceptron with FPGA implementation

被引:0
|
作者
Wang, QR [1 ]
Yi, B [1 ]
Xie, Y [1 ]
Liu, BR [1 ]
机构
[1] Guangdong Univ Technol, Fac Automat, Guangzhou 510080, Peoples R China
来源
2003 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS, VOLS 1-5, CONFERENCE PROCEEDINGS | 2003年
关键词
neural networks; perceptron; FPGA; VHDL; Top-Down;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Most commonly, neural networks's models or algorithms are simulated and implemented by computer programming in neural networks theory research. But in many practical applications, it is necessary to consider essential issues such as hardware implementation. Specific application of neural networks hardware has the advantages of high speed, small in size, good performance and low cost. Thus, the implementation of high performance neural networks hardware is the final target in some actual applications. In this paper, a hardware structure of single perceptron that serves as the basic nerve cell and its implementation method with FPGA is introduced. It is based on VLSI implementation approach for the standard neural networks. The method proposed is a primary discussion and research for the hardware implementation of artificial neural networks.
引用
收藏
页码:762 / 767
页数:6
相关论文
共 50 条
  • [41] Hardware Implementation of IP Packet Filtering in FPGA
    Cholakoska, Ana
    Efnusheva, Danijela
    Kalendar, Marija
    PROCEEDINGS OF THE 7TH INTERNATIONAL CONFERENCE ON APPLIED INNOVATIONS IN IT, VOL 7, ISSUE 1, 2019, 7 (01): : 23 - 29
  • [42] Optimization for Efficient Hardware Implementation of CNN on FPGA
    Farrukh, Fasih Ud Din
    Xie, Tuo
    Zhang, Chun
    Wang, Zhihua
    PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, TECHNOLOGIES AND APPLICATIONS (ICTA 2018), 2018, : 88 - 89
  • [43] Hardware implementation of metaheuristics through LabVIEW FPGA
    Ortiz, Alexandro
    Mendez, Efrain
    Balderas, David
    Ponce, Pedro
    Macias, Israel
    Molina, Arturo
    APPLIED SOFT COMPUTING, 2021, 113
  • [44] FPGA hardware implementation scheme for AQM algorithm
    Yang, Xiao-Ping
    Zheng, Nan
    Chen, Hong
    Wang, Ya-Jun
    Jilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition), 2013, 43 (02): : 472 - 479
  • [45] Hardware Accelerator Implementation on FPGA for Video Processing
    Wong, Kenneth Part Kong
    Yap, VooiVoon
    Teh, Peh Chiong
    2013 IEEE CONFERENCE ON OPEN SYSTEMS (ICOS), 2013, : 47 - 51
  • [46] FPGA hardware implementation of the LZMA compression algorithm
    College of Integrated Circuits, Southeast University, Nanjing
    210018, China
    不详
    210018, China
    Beijing Hangkong Hangtian Daxue Xuebao, 3 (375-382):
  • [47] Hardware Implementation for a Hand Recognition System on FPGA
    Wang, Zhiyuan
    PROCEEDINGS OF 2015 IEEE 5TH INTERNATIONAL CONFERENCE ON ELECTRONICS INFORMATION AND EMERGENCY COMMUNICATION, 2015, : 34 - 38
  • [48] Hardware Implementation of Spiking Neural Networks on FPGA
    Han, Jianhui
    Li, Zhaolin
    Zheng, Weimin
    Zhang, Youhui
    TSINGHUA SCIENCE AND TECHNOLOGY, 2020, 25 (04) : 479 - 486
  • [49] Low power CNN hardware FPGA implementation
    Hareth, Sherry
    Mostafa, Hassan
    Shehata, Khaled Ali
    31ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS (IEEE ICM 2019), 2019, : 162 - 165
  • [50] Hardware implementation of FTC of induction machine on FPGA
    Boukadida S.
    Gdaim S.
    Mtibaa A.
    1600, University of Banja Luka, Faculty of Electrical Engineering (20): : 76 - 84