共 50 条
- [21] Design of Reconfigurable FIR Filter System Based on FPGA MATERIALS SCIENCE AND INFORMATION TECHNOLOGY, PTS 1-8, 2012, 433-440 : 4669 - 4674
- [24] An efficient arithmetic unit based on residue number system COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING, 2002, : 1 - 4
- [26] Low Power FIR Filter implementation on FPGA using Parallel Distributed Arithmetic 2015 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2015,
- [27] Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic International Journal of Speech Technology, 2020, 23 : 549 - 557
- [28] Area-time performance of VLSI FIR filter architectures based on residue arithmetic 23RD EUROMICRO CONFERENCE - NEW FRONTIERS OF INFORMATION TECHNOLOGY, PROCEEDINGS, 1997, : 576 - 583
- [29] Area-efficient FIR filter design on FPGAs using distributed arithmetic 2006 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, VOLS 1 AND 2, 2006, : 248 - +