Area-time performance of VLSI FIR filter architectures based on residue arithmetic

The area-time optimization of a particular class of Residue Number System (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A . T-2 product. The A . T-2 performance models include the binary-to-residue and residue-to-binary conversion complexity. In, particular, efficient Chinese Remainder Theorem (CRT) architectures are derived, based on. Multiply-by-Constant Units (MCUs), which are systematically designed by an introduced methodology. The A . T-2 performance of the derived residue FIR filter architectures, is found to surpass equivalent binary structures, under certain conditions.