Efficient path selection for delay testing based on partial path evaluation

被引:27
|
作者
Tani, S [1 ]
Teramoto, M [1 ]
Fukazawa, T [1 ]
Matsuhiro, K [1 ]
机构
[1] NTT, Opt Network Syst Labs, Yokosuka, Kanagawa 2390847, Japan
关键词
D O I
10.1109/VTEST.1998.670867
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage.
引用
收藏
页码:188 / 193
页数:6
相关论文
共 50 条
  • [1] Efficient path selection for delay testing based on path clustering
    Tani, S
    Teramoto, M
    Fukazawa, T
    Matsuhiro, K
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 15 (1-2): : 75 - 85
  • [2] Efficient Path Selection for Delay Testing Based on Path Clustering
    Seiichiro Tani
    Mitsuo Teramoto
    Tomoo Fukazawa
    Kazuyoshi Matsuhiro
    Journal of Electronic Testing, 1999, 15 : 75 - 85
  • [3] Evaluation of delay testing based on path selection
    Fukunaga, M
    Kajihara, S
    Takeoka, S
    Yoshimura, S
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (12) : 3208 - 3210
  • [4] A flexible path selection procedure for path delay fault testing
    Pomeranz, I
    Reddy, SM
    17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 152 - 159
  • [5] A critical path selection method for delay testing
    Padmanaban, S
    Tragoudas, S
    INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS, 2004, : 232 - 241
  • [6] On effective criterion of path selection for delay testing
    Fukunaga, M
    Kajihara, S
    Takeoka, S
    Yosimura, S
    ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 757 - 762
  • [7] Recursive Path Selection For Delay Fault Testing
    Chung, Jaeyong
    Abraham, Jacob A.
    2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2009, : 65 - 70
  • [8] An adaptive path selection method for delay testing
    Jone, WB
    Yeh, WS
    Yeh, CW
    Das, SR
    IMTC/2000: PROCEEDINGS OF THE 17TH IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE: SMART CONNECTIVITY: INTEGRATING MEASUREMENT AND CONTROL, 2000, : 212 - 216
  • [9] An adaptive path selection method for delay testing
    Jone, WB
    Yeh, WS
    Yeh, CW
    Das, SR
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2001, 50 (05) : 1109 - 1118
  • [10] False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
    Liou, JJ
    Krstic, A
    Wang, LC
    Cheng, KT
    39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 566 - 569