Evaluation of delay testing based on path selection

被引:0
|
作者
Fukunaga, M [1 ]
Kajihara, S
Takeoka, S
Yoshimura, S
机构
[1] Kyushu Inst Technol, Grad Sch Comp Sci & Syst Engn, Iizuka, Fukuoka 8208502, Japan
[2] Matsushita Elect Ind Co Ltd, Semi Co, Nagaoka, Niigata 6178520, Japan
关键词
delay testing; path delay fault; path selection; untestable path;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Since a logic circuit often has too many paths to test delay of all paths, it is necessary for path delay testing to limit the number of paths to be tested. The paths to be tested should have large delay because such paths more likely cause a fault. Additionally, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate two typical criteria of path selection for path delay testing. From our experiments, we observe that test patterns for the longest paths cannot cover many local delay defects such as transition faults.
引用
收藏
页码:3208 / 3210
页数:3
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