A scalable pipelined architecture for separable 2-D discrete wavelet transform

被引：0

作者：

Jou, JM ^{[1
]}

Chen, PY ^{[1
]}

Shiau, YH ^{[1
]}

Liang, MS ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan, Taiwan

来源：

PROCEEDINGS OF ASP-DAC '99: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1999 | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for the computation of 2-D DWT. With these properties, it is easily scalable for different filter lengths and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.

引用

页码：205 / 208

页数：4

共 50 条

[1] A scalable architecture for 2-D discrete wavelet transform
Limqueco, JC
Bayoumi, MA
[J]. VLSI SIGNAL PROCESSING, IX, 1996, : 369 - 377
[2] A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform
Jimmy C. Limqueco
Magdy A. Bayoumi
[J]. Journal of VLSI signal processing systems for signal, image and video technology, 1998, 18 : 125 - 140
[3] A VLSI architecture for separable 2-D Discrete Wavelet Transform
Limqueco, JC
Bayoumi, MA
[J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1998, 18 (02): : 125 - 140
[4] Flipping Based High Performance Pipelined VLSI Architecture for 2-D Discrete Wavelet Transform
Todkar, Swati
Shastry, P. V. S.
[J]. PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON APPLIED AND THEORETICAL COMPUTING AND COMMUNICATION TECHNOLOGY (ICATCCT), 2015, : 832 - 836
[5] A new architecture for the 2-D discrete wavelet transform
Truong, TK
Hung, KC
Huang, YJ
Tseng, YS
[J]. 1997 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2: PACRIM 10 YEARS - 1987-1997, 1997, : 481 - 484
[6] Bit-serial Systolic Architecture for 2-D Non-separable Discrete Wavelet Transform
Mohanty, Basant K.
Meher, Pramod K.
[J]. PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009), 2009, : 288 - +
[7] Bit-Serial Systolic Architecture for 2-D Non-Separable Discrete Wavelet Transform
Mohanty, Basant Kumar
Meher, Pramod Kumar
[J]. ICIAS 2007: INTERNATIONAL CONFERENCE ON INTELLIGENT & ADVANCED SYSTEMS, VOLS 1-3, PROCEEDINGS, 2007, : 1355 - +
[8] A novel VLSI architecture for 2-d discrete wavelet transform
Liu Hong-jin
Shao Yang
He Xing
Zhang Tie-jun
Wang Dong-hui
Hou Chao-huan
[J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 40 - 43
[9] An efficient architecture for the 2-D biorthogonal discrete wavelet transform
McCanny, P
Masud, S
McCanny, J
[J]. 2001 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL III, PROCEEDINGS, 2001, : 314 - 317
[10] A programmable VLSI architecture for 2-D discrete wavelet transform
Chen, CY
Yang, ZL
Wang, TC
Chen, LG
[J]. ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL I: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 619 - 622

← 1 2 3 4 5 →