A scalable pipelined architecture for separable 2-D discrete wavelet transform

被引：0

作者：

Jou, JM ^{[1
]}

Chen, PY ^{[1
]}

Shiau, YH ^{[1
]}

Liang, MS ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan, Taiwan

来源：

PROCEEDINGS OF ASP-DAC '99: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1999 | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for the computation of 2-D DWT. With these properties, it is easily scalable for different filter lengths and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.

引用

页码：205 / 208

页数：4

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