Characterization of Locked Sequential Circuits via ATPG

被引:12
|
作者
Duvalsaint, Danielle [1 ]
Liu, Zeye [1 ]
Ravikumar, Ananya [2 ]
Blanton, Ronald D. [1 ]
机构
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
[2] PES Univ, Dept Elect & Commun Engn, Bangalore, Karnataka, India
关键词
Hardware Security; Logic Locking; Obfuscation;
D O I
10.1109/ITC-Asia.2019.00030
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Hardware security-related threats such as the insertion of malicious circuits, overproduction, and reverse engineering are of increasing concern in the IC industry. To mitigate these threats, various design-for-trust techniques have been developed, including sequential logic locking. Sequential logic locking protects a non-scanned design by employing a key-controlled entrance FSM, key-controlled transitions, or a combination of both techniques. Current methods for characterizing (attacking) the security of sequentially locked circuits do not have the scalability to be applicable to modern circuits. In addition, current methods often require the use of an oracle, which is a working, unlocked circuit that is assumed to be fully initializable and controllable. In this work, an oracle-free, ATPG-based approach is proposed for characterizing the security of a locked sequential circuit. This method is of several in a tool box called CLIC-A (Characterization of Locked ICs via ATPG). Experiments using CLIC-A demonstrate it is effective at recovering the key sequence from various sequentially locked circuits that have been locked using different locking methods.
引用
收藏
页码:97 / 102
页数:6
相关论文
共 50 条
  • [31] A new ATPG technique (ExpoTan) for testing analog circuits
    Varaprasad, B. K. S. V. L.
    Patnaik, L. M.
    Jamadagni, H. S.
    Agrawal, V. K.
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (01) : 189 - 196
  • [32] An Effective Algorithm of Sequential ATPG Based on Improved PSO
    Fei, Wang
    Ming, Zhang
    Ning, Cao
    [J]. PROCEEDINGS OF THE SECOND INTERNATIONAL SYMPOSIUM ON TEST AUTOMATION & INSTRUMENTATION, VOL. 3, 2008, : 1324 - 1328
  • [33] Optimization of phase-locked loop circuits via geometric programming
    Colleran, DM
    Portmann, C
    Hassibi, A
    Crusius, C
    Mohan, SS
    Boyd, S
    Lee, TH
    Hershenson, MD
    [J]. PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 377 - 380
  • [34] Using functional information and strategy switching in sequential ATPG
    Park, JH
    Mercer, MR
    [J]. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1996, : 254 - 260
  • [35] Can SAT be used to improve sequential ATPG methods?
    Prasad, MR
    Hsiao, MS
    Jain, J
    [J]. 17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 585 - 590
  • [36] Sequential spectral ATPG using the wavelet transform and compaction
    Devanathan, SK
    Bushnell, ML
    [J]. 19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 407 - 412
  • [37] An ATPG-based framework for verifying sequential equivalence
    Huang, SY
    Cheng, KT
    Chen, KC
    Glaeser, U
    [J]. INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 865 - 874
  • [38] ON THE OVER-SPECIFICATION PROBLEM IN SEQUENTIAL ATPG ALGORITHMS
    CHENG, KT
    MA, HKT
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (10) : 1599 - 1604
  • [39] Approximate equivalence verification of sequential circuits via genetic algorithms
    Corno, F
    Reorda, MS
    Squillero, G
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 754 - 755
  • [40] The application of learning algorithm of neural networks for ATPG in integrate circuits
    Kang, L
    Li, Z
    Xu, CP
    [J]. ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 1692 - 1695